/**
 * Test bench for alu.v
 **/

module tb;
   reg [3:0] op;
   reg [31:0] op1;
   reg [31:0] op2;
   wire [32:0] result;
   Alu alu1(.op(op), .operand1(op1), .operand2(op2), .result(result));

   initial begin
      $dumpfile("test_alu.vcd");
      $dumpvars(0, tb);
   end

   initial begin
      $monitor ("TIME = %g, op = %d, op1 = %d, op2 = %d result = %d",
                $time, op, op1, op2, result);
      op = 4'b0000;
      op1 = 5;
      op2 = 3;
      #2 op = 4'b0001;
      op1 = 7;
      #2 op1 = 1;
      #2 op = 4'b0010;
      op1 = 32'h89ABCDEF;
      op2 = 32'h1234567;
      #2 op = 4'b0011;
      #2 $finish;
   end // initial begin

endmodule
